verilog HDLBits刷题[Shift Registers]“Exams/ece241 2013 q12”---3-input LUT

1、题目In this question, you will design a circuit for an 8x1 memory, where writing to the memory is accomplished by shifting-in bits, and reading is random access, as in a typical RAM. You will then use the circuit to realize a 3-input logic function.First, create an 8-bit shift register with 8 D-type flip-flops. Label the flip-flop outputs from Q[0]...Q[7]. The shift register input should be calledS, which feeds the input of Q[0] (MSB is shifted in first). Theenableinput controls whether to shift. Then, extend the circuit to have 3 additional inputsA,B,Cand an outputZ. The circuits behaviour should be as follows: when ABC is 000, ZQ[0], when ABC is 001, ZQ[1], and so on. Your circuit should contain ONLY the 8-bit shift register, and multiplexers. (Aside: this circuit is called a 3-input look-up-table (LUT)).2、代码module top_module ( input clk, input enable, input S, input A, B, C, output Z ); reg [7:0]Q; wire [2:0]addr; always(posedge clk)begin if(enable) Q{Q[6:0],S}; else QQ;//防锁存 end assign addr{A,B,C}; assign ZQ[addr]; endmodule3、结果