verilog HDLBits刷题[Finite State Machines]“Fsm1”---Simple FSM1(synchronous reset)

1、题目This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.This exercise is the same as fsm1, but using synchronous reset.2、代码// Note the Verilog-1995 module declaration syntax here: module top_module(clk, reset, in, out); input clk; input reset; // Synchronous reset to state B input in; output out;// reg out; // Fill in state name declarations parameter A1b0,B1b1; reg present_state, next_state; always(*)begin case(present_state) A:next_statein?A:B; B:next_statein?B:A; endcase end always (posedge clk) begin if (reset) begin present_stateB; end else begin present_statenext_state; end end assign out(present_stateB); endmodule3、结果